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Edge detection is an important and growing area in different fields such as image pattern recognition, machine learning and processing, and Computer vision. Edge detection of an image of the object is the main goal for different Edge detection algorithms. In Edge detection, the most important step is to identify the edges of an image of the object and pixel information of the Image In every edge detection algorithm. There will be 2 types of masks one in the horizontal direction and the other in the vertical direction. The kernel or mask is a convolution vector of the nXn matrix which is multiplied by the sub-window of an image. The effective and efficient performance of a digital system mainly depends on the delay, area, and power consumption. These parameters decide the efficiency of any digital core system. This project converts the image pixel information to binary for processing with different edge detection algorithms like Canny, Sobel, Prewitt, and Roberts. The algorithms are then simulated and synthesized on FPGA with the targeted device xc3s4000-4fg900. The input image with resolution 256X256 is given as input to the MATLAB version 2014a. The MATLAB code converts image pixel intensity information to binary form as hardware input can only be in binary not the pixel intensity information, so we use MATLAB software to convert pixel intensity information to a hexadecimal value which is given as input to the model sim version 6.4a. The Different edge detection algorithm like Sobel, Canny, Prewitt, and Robert is implemented using Verilog HDL, the model sim is used for simulation, and synthesis is performed using Xilinx software. The design parameters results obtained for different edge detection algorithms are compared, The Generated text file is sent to MATLAB software for the extraction of edges. and synthesis is performed in the Xilinx platform to generate a synthesis report for RTL schematic and Technology Schematic with a target device xc3s4000-4fg900. The Proposed methodology gives better performance with fewer lut’s of 119, slices 77, gates 1736, overall delay 28.121ns, gate delay 15.304ns, and path delay 12.817ns along with 0 block ram and 0 distributed ram.